The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor integrated circuit device in a standard cell system which can be designed to provide a high speed large scale integrated circuit (LSI) with dynamic circuits within a short period. A method for designing it is also disclosed.
A high speed logic LSI with dynamic precharged circuits has been discussed in ISSCC Digest of Technical Papers, 1987, p. 62. Also, the speed-up technique using precharged circuits has been discussed in Symposium on VLSI Technology, Digest of Technical Papers, pp. 93, 1987, and JPA-62-98827. Moreover, shortening of a designing period by means of a design automation system has been disclosed in Proceedings of ICCC, 1982, pp. 512-515.
The high speed operation of a circuit with complicated logic capability using a precharged circuit according to the above prior art can be realized. In designing such as LSI using this circuit, however, it was necessary to pay attention to the following items, and, it correspondingly, was difficult to apply such a standard cell system to it.
(1) If there is capacitive coupling between dynamic nodes within circuit and signal operations adjacent thereto influence the dynamic nodes, the potentials of the dynamic nodes being changed due to potential changes in the wirings in circuit operation. This may reduce the operation margin of the circuit and further cause the malfunction thereof. In making the layout of cells, therefore, it is necessary to pay attention to the electro-static capacitance between wiring within such a cell and its dynamic node.
(2) For the same reason as above, it is impossible to pass the signal wirings above the cells with such precharged circuits.
(3) It is necessary to supply all the cells using the precharged circuits with clock signals with the same phase.
As regards the above item (1), in designing the layout of various kinds of unit cells required to design LSI, the work therefor must be advanced while paying attention to the item (1) for each cell. This makes it difficult to automate the work and thus it takes a very long time to design LSI. Also, if the rule of the layout, the process, etc. are varied, the amount of work required to modify the layout of the unit cells will be enormous. Further, in the step of arranging a great number of unit cells thus formed and making wirings therefor to complete LSI, the above fact of (2) is a great obstacle to the automatic wiring using the DA (design automation) technique. Moreover, for the item (3), it is necessary to carefully design the system of supplying clock signals for the entire LSI chip. This is also an obstacle to the design automation.
Furthermore, JPA-63-160241 discloses a semiconductor integrated circuit in a standard system in which a wiring inhibiting area is located at least on the output node of a dynamic cell in a dynamic operation. The technique, however, is disadvantageous in the integration or packaging density, and also the above wiring inhibiting area is an obstacle to the automatic wiring using the design automation technique.